1. Field of the Invention
The present invention relates to ceramic multilayer substrate in which a connection between internal patterns and an external terminal is stably achieved, and a method for manufacturing the substrate, and more particularly to a low temperature co-fired ceramic multilayer substrate in which internal connection parts formed in the internal patterns are broader enough to surround the external terminal, and a method for manufacturing the substrate, thereby stably achieving a connection between the internal patterns and the external terminal and maintaining the connection even in the case of an error occurring in a step for forming a through hole on the substrate.
Further, the present invention relates to a low temperature co-fired ceramic multilayer substrate in which the internal connection part not being connected to the external terminal is not exposed at the outer surface of the substrate, and a method for manufacturing the substrate, thereby not breaking a vacuum state generated within a space for mounting a surface acoustic wave filter chip within the substrate and preventing cracks from forming on the outer surface of the substrate.
2. Description of the Related Art
A technique for manufacturing a low temperature co-fired ceramic (hereinafter, being referred to as “LTCC”) substrate is a process in which an internal electrode and passive elements (R, L, and C) for given circuits are formed a green sheet made of glass ceramic by a screen printing method using a metal with high electric conductivity such as Ag, Cu, or etc., and a plurality of the green sheets are stacked vertically and then fired (generally at less than 1,000° C.) so as to manufacture MCM (multi-chip modules) and multi-chip packages.
Since the ceramic substrate and the metallic elements are co-fired, the LTCC technique can form the passive elements (R, L, and C) within a module, thereby obtaining a complex configuration including many components and being advantageous in terms of miniaturization.
Since the LTCC substrate comprises the embedded passive elements, the LTCC substrate can be formed as a SOP (System-On-Package), thereby minimizing a parasitic effect generated in SMD (Surface Mounted Device) type components. Further, the LTCC substrate reduces electrical noise generated at soldering parts in surface mounting, thereby improving electrical characteristics of the manufactured device, and reduces the number of solderings, thereby improving the reliability of the manufactured device. Moreover, the LTCC substrate minimizes a temperature coefficient of resonant frequency (Tf) by adjusting a thermal expansion coefficient, thereby controlling characteristics of a dielectric resonator.
The LTCC multilayer substrate is formed by forming circuits in a single ceramic substrate and vertically stacking a plurality of the ceramic substrates. Therefore, external terminals to be connected to the outside must be formed on an outer surface of the LTCC substrate and electrically connected to circuit patterns within the substrate.
As shown in FIG. 1, a method for manufacturing a ceramic electronic component is disclosed by Japanese Patent Laid-open Publication No. Hei6-215982. Conventionally, when components made of dielectric or magnetic material are formed on a ceramic substrate adjacent to via holes formed through the ceramic substrate, the material flows into the via holes and finally seals the via holes. Further, in case that the material within the via holes is sucked from one ends of the via holes so as to form external electrodes at the internal surfaces of through holes, air flow into the via holes is dispersed by a difference of cross sectional areas of the via holes of each layer and the external electrode is non-uniformly deposited on the inner wall of the via hole. Therefore, these problems are solved by the method for manufacturing a ceramic electronic component disclosed by the above Japanese Publication.
In the above Japanese Publication, a base substrate 7 provided with a plurality of via holes formed therethrough is prepared. A ceramic stack structure 8 having internal electrodes embedded therein is formed on the base substrate 7 so as to block the via holes of the base substrate 7. A plurality of through holes are formed on the ceramic stack structure 8 so as to correspond to the via holes of the base substrate 7, and an external electrode 10 is formed in the through hole.
In the aforementioned structure disclosed by Japanese Patent Laid-open Publication No. Hei6-215982, a connection between the external electrode 10 and the internal electrode 9 is obtained by a line contact, thereby producing a small contact area. Since the connection between the internal electrode 9 and the external terminal 10 is unstable, stability of signal input/output is reduced and a defective proportion of manufactured products is increased by an error in the process. Since the internal electrodes 9 are first formed within the ceramic stack structure 8, and then the through hole is formed on the structure 8 and the external electrode 10 is formed in the through hole, as shown in FIGS. 2A and 2B, in case a connection part between the internal electrode 9 and the external electrode 10 is small, the internal electrode 9 may be electrically blocked during a step for forming the though hole, or plating the through hole or the electrical connection between the internal electrode 9 and the external electrode 10 may be unstable. FIG. 2a shows the ceramic substrate with the through hole, and FIG. 2b shows the ceramic substrate without the through hole.
Further, when the position of the through hole is shifted by an error generated in the process, the contact area between the internal electrode 9 and the external electrode 10 is changed, and more severely the internal electrode 9 is not connected to the external electrode 10. Therefore, a defective proportion of the manufactured products is increased and the quality of the products is not easily controlled.